Silicon (Si), gallium arsenide (GaAs), and the like, are conventionally known as a semiconductor material for high-frequency devices. Recently, the field of use of high-frequency devices is rapidly expanding. The high-frequency devices are accordingly more often used under severe environments such as a high temperature environment. Therefore, achievement of a high-frequency device that is able to withstand a high temperature environment is one of important problems from the viewpoint of a reliable operation, processing of a large amount of information, and improvement in the controllability in wide ranges of applications and environments.
Silicon carbide (SiC) is of interest as one of materials that can be used for manufacturing a semiconductor wafer having an excellent heat resistance. SiC has an excellent mechanical strength and a radiation hardness. Moreover, adding impurities to SiC enables a valence electron such as an electron or a hole to be easily controlled, and SiC is characterized in a wide band gap (about 3.0 eV in 6H monocrystalline SiC; 3.2 eV in 4H monocrystalline SiC), a high breakdown field (2.8 MV/cm in 4H monocrystalline SiC, which is about ten times that of Si and GaAs), and a high saturated drift velocity of electrons (2.2×107 cm/s in 4H monocrystalline SiC, which is about twice that of Si). This is why SiC is expected as a material for a next-generation power device that achieves a high-temperature resistance, high frequency resistance, high voltage resistance, and high environment resistance, which cannot be achieved by the existing semiconductor material described above.
A method for manufacturing a semiconductor wafer using SiC, including forming an epitaxial layer, has been conventionally known. This type of manufacturing method is disclosed in, for example, Patent Documents 1 to 3.
In the Patent Document 1, a SiC epitaxial layer is formed through a CVD (Chemical Vapor Deposition) process. In the step of causing an epitaxial growth, a defect suppression layer, which is formed at a reduced growth rate of 1 μm or less per hour, is introduced, thus enabling formation of a SiC epitaxial layer containing a smaller amount of defects.
The Patent Document 2 discloses the following method for forming a SiC epitaxial layer. The method for forming a SiC epitaxial layer includes the steps of: causing a SiC bulk crystal to grow by using the technique of seed crystal addition and sublimation; and causing a liquid-phase epitaxial growth on a surface of the bulk crystal. In the step of causing the liquid-phase epitaxial growth, a melting growth is caused so that a micropipe defect having propagated from the seed crystal to the substrate of the bulk crystal is closed, which achieves formation of a SiC epitaxial layer containing a smaller amount of micropipe defects.
In the Patent Document 3, a metastable solvent epitaxy (MSE) process is disclosed as a method for causing a close-spaced liquid-phase epitaxial growth of monocrystalline SiC. The MSE process is a method in which: a seed substrate made of monocrystalline SiC and a carbon feed substrate having a higher free energy than that of the seed substrate are arranged opposed to each other, and a Si melt layer serving as a solvent (carbon transfer medium) is interposed between the seed substrate and the carbon feed substrate; and then, the seed substrate and the carbon feed substrate are subjected to a heat treatment in a high-temperature vacuum environment, thus causing an epitaxial growth of monocrystalline SiC on a surface of the seed substrate.